NAND flash memories are used widely as mass storage memory devices. In recent years, memory devices have been miniaturized for cost reduction and increased capacity per bit, and further miniaturization is a great demand in this technical field. However, before proceeding miniaturization of flash memories, there are many issues to be solved such as development of lithography techniques and inhibition of short channel effect, interdevice interference, and interdevice variations. Thus, a miniaturization technique simply directed to improvement of a plane structure will not be enough to sustainably increase storage density of memory devices in future.
Considering the above, techniques to shift such a conventional two-dimensional (plane) structure to a three-dimensional (solid) structure have been developed in recent years for higher memory cell integration, and various kinds of three-dimensional nonvolatile semiconductor storage devices have been proposed. One of them is a vertical gate (VG) semiconductor memory structure which includes a fin with stacked semiconductor layers (active areas) on each of which a NAND string is arranged.
The VG semiconductor memory structure has a layout substantially similar to that of a two-dimensional NAND including peripheral devices and the like, and contacts corresponding to the semiconductor layers and gate contacts can be formed therein at the same time.
The VG semiconductor memory structure can be classified broadly into two types by its memory cell structure. One is a vertical gate-floating gate (VG-FG) type in which charge storage layers are electrically floating, and the other is a vertical gate-metal/oxide/nitride/oxide/silicon (VG-MONOS) type in which charge storage layers trap the charge.
In the VG-FG type, the charge storage layer must be provided independently memory cell by memory cell for proper function of the memory device. In the VG-MONOS type, the charge storage layer must be separated memory cell by memory cell, especially, in the direction of extension of the NAND string (extension of the fin) for improved performance of the memory device.
Considering these points, the separation of the charge storage layer in the direction of extension of the NAND string is performed at the same time when the control gate is patterned into lines and spaces using a hard mask preliminarily formed on the fin as a mask.
However, the hard mask is also used to process the fin. Thus, the width of the hard mask must be shrunk to an optimal value necessary for self-aligned separation of the charge storage layer after the fin is processed but before the control gate is patterned into lines and spaces.
Such a hard mask shrink is performed by isotropic etching and conventionally, there has been a problem that the initial thickness of the hard mask must be large enough before the etching. The hard mask whose thickness is large enough becomes a part of the fin (the uppermost layer) and enlarges the height of the fin. Thus, the aspect ratio of a trench between adjacent fins is enlarged and consequently, the degree of difficulty in forming memory cells on each semiconductor layer increases.
Furthermore, the controllability is not good in the hard mask shrink by isotropic etching. In that case, a process margin in separating the charge storage layer, that is, the amount of shrink must be preset relatively large. Due to this process margin, the width of the fin between the control gates becomes partly very narrow. To prevent this, the initial width of the fins must be set wide (which is disadvantageous to the miniaturization purpose). They are problems in this technical field, too.